Field-effect transistor and manufacturing method thereof

ABSTRACT

Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate&#39;s upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority from Korean PatentApplication No. 10-2010-0130291, filed on Dec. 17, 2010, with the KoreanIntellectual Property Office, the disclosure of which is incorporatedherein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transistor, and more particularly toa field-effect transistor and a manufacturing method thereof, in which aseparate lithography process and its corresponding additional processare not required, and insulating films below field electrodes havedifferent thicknesses.

2. Description of the Prior Art

FIGS. 1A to 1H are views illustrating a method for manufacturing afield-effect transistor, according to a prior art.

As shown in FIG. 1A, on a semiconductor substrate 10 including galliumnitride (GaN), silicon (Si), silicon carbide (SiC), semi-insulatinggallium arsenide (GaAs), etc., an active layer 11 and a cap layer 12 aresequentially formed. For example, in a case of a high electron mobilitytransistor (HEMI) element using hetero junction of aluminum galliumnitride (AlGaN) and gallium nitride (GaN), the active layer 11 includesa gallium nitride buffer layer and an aluminum gallium nitride barrierlayer, and the cap layer 12 includes a gallium nitride (GaN) layer.

As shown in FIG. 1B, a region where a source•drain ohmic metal layer 13is to be formed is defined as a source•drain pattern. On the uppersurface of the cap layer 12, an ohmic metal is deposited and then thesource•drain ohmic metal layer 13 is formed through rapid thermalannealing (RTA), etc. For example, in a manufacturing process of an HEMIelement using a gallium nitride (GaN)-based compound semiconductor, asan ohmic metal, a metal layer formed by sequentially depositing a Tifilm, an Al film, a Ni film, an Au film, etc. with a predeterminedthickness is used. In a process of manufacturing an HEMI element, ametal semi-conductor field effect transistor (MESFET), or the like byusing a gallium arsenide (GaAs)-based compound semiconductor, a metallayer formed by sequentially depositing an AuGe film, a Ni film, an Aufilm, etc. with a predetermined thickness is used as an ohmic metal.

As shown in FIG. 1C, on the cap layer 12 which has been subjected to anohmic process, a photosensitive film is coated, and then gate patterns14 a, 14 b and 14 c formed with a T-shaped hole 15 a are formed by usingoptical lithography, e-beam lithography or the like. Herein, the gatepatterns 14 a, 14 b and 14 c are used to manufacture a T-shaped gateelectrode while reducing a gate width without an increase in aresistance of a gate electrode.

As shown in FIG. 1D, a gate recess process for etching the cap layer 12exposed through the T-shaped hole 15 a is performed so as to form a gaterecess region 15 b to be deposited with a gate metal. Herein, the gaterecess process is the most critical step in manufacturing of an HEMTelement or an MESFET element using a compound semiconductor, and isgenerally performed while measuring a current. Also, the processincludes one or more steps including a wet process, a dry process or acombination of the wet and dry processes. The gate recess process isperformed using a gas such as CF₄, BCl₃, Cl₂ and SF₆ in an apparatus fordry etching such as an electron cyclotron resonance (ECR) or inductivecoupled plasma (ICP). Herein, the process is carried out by usingvarious wet etching solutions such as a phosphoric acid-based solutionin which H₃PO₄, H₂O₂ and H₂O applied to a gallium arsenide (GaAs)-basedcompound semiconductor element are mixed at a predetermined ratio.

As shown in FIG. 1E, a gate metal is deposited on the gate patterns 14a, 14 b, and 14 c, and the gate patterns 14 a, 14 b, and 14 c areremoved by a lift-off process, thereby forming a T-shaped gate electrode16. For example, in the manufacturing process of the HEMI element usinga gallium nitride (GaN)-based compound semiconductor, the gate electrode16 is formed by sequentially depositing metal layers such as a Ni film,and an Au film to a predetermined thickness. In the manufacturingprocess of an HEMI element, an MESFET element, or the like using agallium arsenide (GaAs)-based compound semiconductor, the gate electrode16 is formed by sequentially depositing metal layers such as a Ti film,a Pt film, an Au film, etc. to a predetermined thickness.

As shown in FIG. 1F, after the gate electrode 16 is formed, on the caplayer 12's upper portion including the source•drain ohmic metal layer 13and the T-shaped gate electrode 16, an insulating film 17 is deposited.Then, as shown in FIG. 1G, through the performance of a lithographyprocess for forming a field electrode, a field electrode pattern 18 isformed.

As shown in FIG. 1H, after a metal is deposited on the field electrodepattern 18 for forming a field electrode, and the field electrodepattern 18 is removed by a lift-off process, thereby forming a pluralityof field electrodes 19. In this case, for the plurality of fieldelectrodes 19, the thickness of the insulating film 17 below the fieldelectrodes 19 is fixed as a predetermined thickness. In a case where thethickness of the insulating film 17 below each of the field electrodes19 is adjusted, a separate mask pattern for each of the field electrodes19 is required and thus, a lithography process, an etching process, ametal-deposition process and a lift-off process are performed.

As described above, in a case of a conventional field-effect transistorincluding a field electrode, and a manufacturing method thereof, inmanufacturing of the field electrode, a peak value may be reducedthrough field reduction in a region of a gate and a drain. Furthermore,it is possible to achieve a high breakdown voltage through a reductionof leakage current of a gate while maintaining high frequencyperformance and also it is expected that it is possible to reduce acapacitance between a gate and a drain through a shielding effect.Accordingly, it is possible to manufacture a power device which iscapable of being driven at high voltage and high current.

However, in the case of a field-effect transistor including a fieldelectrode, the thickness of an insulating film below field electrodes onone substrate is generally fixed. Thus, in order to adjust the thicknessof the insulating film, a separate mask pattern is required for each ofthe field electrodes. Furthermore, for respective mask patterns, alithography process, an etching process, a metal-deposition process, anda lift-off process have to be repeatedly performed.

For example, in an HEMT element manufactured using a compoundsemiconductor including GaN, GaAs, InP, etc., one or more fieldelectrodes, besides a gate, are manufactured between a source and adrain. In the field electrodes manufactured using a mask pattern forforming the field electrodes, the thickness of an insulating film belowthe field electrodes on one substrate is generally fixed. Thus, in orderto adjust the thickness of the insulating film below each of the fieldelectrodes, a separate mask pattern is required for each of the fieldelectrodes. Furthermore, for respective mask patterns, a lithographyprocess, an etching process, a metal-deposition process, and a lift-offprocess have to be repeatedly performed.

Accordingly, in a case of a conventional manufacturing method of afield-effect transistor including a field electrode, it is impossible toapply different thicknesses of an insulating film below fieldelectrodes, to the same element. Even when the thickness of aninsulating film below field electrodes can be varied, a separate maskpattern is required for each of the field electrodes. Furthermore, forrespective mask patterns, a lithography process, an etching process, ametal-deposition process and a lift-off process have to be repeatedlyperformed. This causes a problem such as an increase in a unit cost of amanufacturing process and a reduction of productivity.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve theabove-mentioned problems occurring in the prior art, and an object ofthe present invention is to provide a field-effect transistor and amanufacturing method thereof, in which a separate lithography processand its corresponding additional process are not required and aninsulating film below field electrodes can have different thicknesses.

In order to accomplish this object, there is provided a method formanufacturing a field-effect transistor, the method including: a mainelectrode forming step for forming a source, a drain and a gateelectrode on an upper portion of a semiconductor substrate; aninsulating film depositing step for depositing an insulating film on thesemiconductor substrate's upper portion including the source, the drain,and the gate electrode; a field electrode pattern forming step forforming a multi-layered field electrode pattern having differentexposure layers of openings by depositing multi-layered photosensitivefilms on an upper portion of the insulating film and patterning thefilms; an insulating film etching step for performing an insulating filmetching process using the field electrode pattern as an etching mask sothat the insulating film has different stepped heights; and a fieldelectrode forming step for depositing a metal layer by using the fieldelectrode pattern and forming field electrodes on the upper portion ofthe insulating film having the different stepped heights throughperformance of a lift-off process.

In accordance with another aspect of the present invention, there isprovided a field-effect transistor including: a semiconductor substrate;a source ohmic metal layer formed on one side of the semiconductorsubstrate; a drain ohmic metal layer formed on another side of thesemiconductor substrate; a gate electrode formed between the sourceohmic metal layer and the drain ohmic metal layer, on an upper portionof the semiconductor substrate; an insulating film formed on thesemiconductor substrate's upper portion including the source ohmic metallayer, the drain ohmic metal layer and the gate electrode; and aplurality of field electrodes formed on an upper portion of theinsulating film, wherein the insulating film below the respective fieldelectrodes has different thicknesses.

In a field-effect transistor including a plurality of field electrodes,according to the present invention, it is possible to adjustcharacteristics of the insulating film below the field electrodes byadjusting the thickness of the insulating film below the respectivefield electrodes. Accordingly, it is possible to apply various biases tothe respective field electrodes, thereby improving the breakdown voltagecharacteristic of an element. Accordingly, it is possible to manufacturea power device which can achieve high power when driven at high voltage.

Also, since separate additional masks are not required in manufacturingof the plurality of field electrodes, it is possible to manufacturehigh-performance transistors with improved productivity, increaseduniformity and increased reproducibility, compared to a conventionalprocess.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIGS. 1A to 1H are views illustrating a method for manufacturing afield-effect transistor according to a prior art; and

FIGS. 2A to 2I are views illustrating a method for manufacturing afield-effect transistor according to one embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described indetail with reference to the accompanying drawings. The configurationand operation effects of the present invention will be clearlyunderstood through the detailed description as below.

FIGS. 2A to 2I are views illustrating a method for manufacturing afield-effect transistor according to one embodiment of the presentinvention.

As shown in FIG. 2A, on a semiconductor substrate 20, an active layer 21and a cap layer 22 are sequentially formed. As shown in FIG. 2B, aregion where a source•drain ohmic metal layer 23 is to be formed isdefined as a source•drain pattern, which is deposited with an ohmicmetal, and then is formed with the source•drain ohmic metal layer 23through rapid thermal annealing (RTA), etc. Herein, in a manufacturingprocess of a high electron mobility transistor (HEMI) element using agallium nitride (GaN)-based compound semiconductor, as an ohmic metal, ametal layer formed by sequentially depositing a Ti film, an Al film, aNi film, an Au film, etc. with a predetermined thickness may be used. Ina manufacturing process of an HEMI element, a metal semi-conductor fieldeffect transistor (MESFET) element, or the like using a gallium arsenide(GaAs)-based compound semiconductor, as an ohmic metal, a metal layerformed by sequentially depositing an AuGe film, a Ni film, an Au film,etc. with a predetermined thickness may be used. Then, a source•drainohmic metal layer may be formed through an RTA process.

Then, as shown in FIG. 2C, on the cap layer 22 which has been subjectedto an ohmic process, a photosensitive film is coated, and then gatepatterns 24 a, 24 b and 24 c formed with a T-shaped hole 25 a are formedby using optical lithography, e-beam lithography or the like.

As shown in FIG. 2D, a gate recess process for etching the cap layer 22exposed through the T-shaped hole 25 a is performed so as to form a gaterecess region 25 b to be deposited with a gate metal. The gate recessprocess is the most critical step in an HEMT element or an MESFETelement using a compound semiconductor and is generally performed whilemeasuring a current. Also, the process includes one or more stepsincluding a wet process, a dry process, or a combination of the wet anddry processes. The gate recess process may be performed using a gas suchas CF₄, BCl₃, Cl₂ and SF₆ in an apparatus for dry etching such as anelectron cyclotron resonance (ECR) or inductive coupled plasma (ICP).Herein, the process is carried out by using various wet etchingsolutions such as a phosphoric acid-based solution in which H₃PO₄, H₂O₂and H₂O applied to a gallium arsenide (GaAs)-based compoundsemiconductor element are mixed at a predetermined ratio.

As shown in FIG. 2E, a gate metal is deposited on the gate patterns 24a, 24 b and 24 c, and the gate patterns 24 a, 24 b and 24 c are removedby a lift-off process, thereby forming a T-shaped gate electrode 26. Forexample, in the manufacturing process of the HEMT element using agallium nitride (GaN)-based compound semiconductor, the gate electrode26 is formed by sequentially depositing metal layers such as a Ni filmand an Au film to a predetermined thickness. In the manufacturingprocess of an HEMT element, an MESFET element, or the like using agallium arsenide (GaAs)-based compound semiconductor, the gate electrode26 is formed by sequentially depositing metal layers such as a Ti film,a Pt film, an Au film, etc. to a predetermined thickness.

As shown in FIG. 2F, after the gate electrode 26 is formed, on the caplayer 22's upper portion including the source•drain ohmic metal layer 23and the gate electrode 26, an insulating film 27 is deposited in one ormore layers. Herein, the insulating film 27 may include a material suchas silicon nitride, silicon oxide, BCB and a porous silica thin film,which protects the surface of the compound semiconductor substrate.

Then, the kind and the thickness of the insulating film 27 may bedetermined in consideration of an etch rate of the insulating film 27and etch rates of photosensitive films in the lowest layer and itsdirectly upper layer from among multi-layered photosensitive films, thephotosensitive films constituting field electrode patterns 28 a, 28 band 28 c used as an etching mask in the insulating film 27's etchingprocess as described below. In other words, it has to be adjusted insuch a manner that the surface of the semiconductor substrate 20 is notexposed and the insulating film can be exposed through etching of thephotosensitive films in an exposure area of the photosensitive films inthe lowest layer or its directly upper layer of the field electrodepatterns 28 a, 28 b and 28 c in the etching process of the insulatingfilm 27 as described below.

As shown in FIG. 2G, after the multi-layered photosensitive films arecoated on the insulating film 27, the field electrode patterns 28 a, 28b and 28 c having different exposure layers of openings 29 a, 29 b and29 c are formed. According to one embodiment of the present invention,when three field electrodes are manufactured, triple or more fieldelectrode patterns 28 a, 28 b, and 28 c are required. Specifically, thefield electrode patterns 28 a 28 b, and 28 c are multi-layeredphotosensitive film patterns in which exposure layers of the openings 29a, 29 b and 29 c are the insulating film 27, the lowest photosensitivefilm 28 a and its directly upper photosensitive film 28 b, respectively.When the field electrode patterns 28 a, 28 b and 28 c are manufacturedby using e-beam lithography, various combinations of multi-layeredphotosensitive films such as PMMA/PMGI/Copolymer/PMMA orZEP/PMGI/Copolymer/ZEP may be used. Herein, the kind and thickness ofthe lowest layer 28 a (hereinafter, “a first photosensitive film”) andits directly upper photosensitive film 28 b (hereinafter, referred to as“a second photosensitive film”) have to be selected in consideration ofetch selectivity in such a manner that the insulating film 27 inexposure areas of the first photosensitive film 28 a and the secondphotosensitive film 28 b can be totally exposed during an etchingprocess of single- or multi-layered insulating films on thesemiconductor substrate 20.

As shown in FIG. 2H, through the performance of an insulating filmetching process using, as an etching mask, field electrode patterns 28a, 28 b and 28 c for manufacturing field electrodes, the insulating film27 has different depths.

In a case of dry etching, the insulating film etching process may beperformed in an apparatus for dry etching such as reactive ion etching(RIE), magnetically enhanced reactive ion etching (MERIE) and ICP, whilein a case of wet etching, the process may be performed by using abuffered oxide etch (BOE) solution, etc.

As shown in FIG. 2I, a metal layer for field electrodes is deposited byusing the field electrode patterns 28 a, 28 b and 28 c for manufacturingthe field electrodes and then a lift-off process is performed so as tomanufacture a plurality of field electrodes 30 a, 30 b and 30 c.

Accordingly, in one embodiment of the present invention, by adjustingthe thickness of the insulating film 27 below the respective fieldelectrodes 30 a, 30 b, and 30 c, it is possible to adjustcharacteristics of the insulating film below the field electrodes.Accordingly, it is possible to apply various biases to the respectivefield electrodes, thereby improving the breakdown voltage characteristicof an element. Accordingly, it is possible to manufacture a power devicewhich can achieve high power when driven at high voltage.

Also, since separate additional masks are not required in manufacturingof the plurality of field electrodes 30 a, 30 b and 30 c, it is possibleto manufacture high-performance transistors with improved productivity,increased uniformity and increased reproducibility, compared to aconventional process.

The embodiments disclosed in the specification of the present inventionare not intended to limit the present invention. It should beappreciated that the scope of the present invention is defined by theclaims as below and various technologies may be made within a scopeequivalent to the scope of the present invention.

What is claimed is:
 1. A field-effect transistor comprising: asemiconductor substrate; a source ohmic metal layer formed on one sideof the semiconductor substrate; a drain ohmic metal layer formed onanother side of the semiconductor substrate; a gate electrode formedbetween the source ohmic metal layer and the drain ohmic metal layer onan upper portion of the semiconductor substrate; an insulating filmformed on the semiconductor substrate's upper portion comprising thesource ohmic metal layer, the drain ohmic metal layer and the gateelectrode; and a plurality of field electrodes formed on an upperportion of the insulating film, wherein the insulating film below therespective field electrodes has different thicknesses.
 2. Thefield-effect transistor as claimed in claim 1, wherein the insulatingfilm comprises at least one selected from the group including siliconnitride, silicon oxide, HfO₂, BCB and a porous silica thin film.
 3. Thefield-effect transistor as claimed in claim 1, wherein a kind and athickness of the insulating film are determined in consideration of anetch rate of the insulating film and etch rates of respectivephotosensitive films, except for an uppermost photosensitive film fromamong the multi-layered photosensitive films used in an insulating filmetching process.